1. Field of the Invention
The present invention relates to a method for fabricating a semiconductor device, and more particularly to a method for fabricating a semiconductor device with a DRAM memory cell having a metal insulator semiconductor type transistor (hereinafter referred to as "MIS" transistor) as a switching element and a stacked capacitor as a data storing element.
2. Description of the Related Art
A conventional memory cell structure of the kind to which the present invention relates is shown in FIGS. 1A through 1D. With reference to these drawings, the sequential fabrication steps thereof are first explained to assist the understanding of the present invention.
FIG. 1A is first referred to. A surface of a p-type silicon substrate 201 is selectively oxidized thereby forming a field oxide film 202 and, thereafter, a gate oxide film 203 is formed by thermal oxidation in regions where the field oxide film 202 is not formed. Then, a gate electrode 204 is formed by depositing polycrystalline silicon with the resulting film being patterned and, by ion-implantation of phosphor (P), highly doped n-type diffusion layers 205a and 205b used as source/drain regions are formed. A surface of the resulting MIS type transistor is covered with a silicon dioxide film 206.
Next, as seen in FIG. 1B, the silicon dioxide film 206 is selectively etched using a lithography technique thereby forming a first contact hole 208 which exposes a surface of the highly doped n-type diffusion layer 205a. This is followed by the formation of a phosphor doped polycrystalline silicon film which is patterned using a lithography technique to form a storage electrode (a first electrode) 210 of a capacitor which is in contact with the highly doped n-type diffusion layer 205a.
Next, as seen in FIG. 1C, on a surface of the storage electrode 210, there is formed by thermal oxidation a dielectric film 211 on which a phosphor doped silicon film is formed and is patterned into desired patterns using a lithography technique to form a second electrode 212 of the capacitor.
Then, on the resulting film, silicon dioxide is deposited to form an interlayer insulating film 213, and this is followed by the selective etching of the interlayer insulating film 213 and also the silicon dioxide film 206 to form a second contact hole 214 which exposes a surface of the highly doped n-type diffusion layer 205b. Finally, a silicide film is formed and patterned to form a bit line 215, which results in the completion of the conventional memory cell having a stacked capacitor as shown in FIG. 1D.
In the conventional memory cell structure having the stacked capacitor described above, it is difficult, in view of advancement of higher integration and miniaturization, to maintain a sufficient fabrication margin or tolerance to electrically insulate the storage electrode of the capacitor from the gate electrode.
Also, with the conventional arrangement, the fact that the area per unit cell stays small makes it difficult to maintain such capacitance of the capacitor that is demanded of the device and, thus, it is desired that a method be developed so as to be able to increase the capacitance of the capacitor without increasing the cell size involved.